MAX11040GUU+T【PDF 11/35 页】IC ADC 24BIT 4CH 38-TSSOP

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MAX11040K/MAX11060

24-/16-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADCs

Maxim Integrated

Sampling Instant Control Register

By default, the devices sample all 4 input channels

simultaneously. To delay the sampling instant on one or

more channels, program the appropriate byte in the

Sampling Instant Control register. The delay of the

actual sampling instant of each individual channel from

the default sampling instant (PHI_[7:0] = 0x00) is

adjustable between 32 to 819,121 XIN clock cycles,

which is 1.3μs to 333μs with fXINCLOCK at 24.576MHz

(see Table 3.)

Configuration Register

The Configuration register contains 5 bits that control the

functionality of the devices. The default state is 0x00.

The data length of the Configuration register is 8 bits

per cascaded device (see Table 4).

Table 3. Sampling Instant Control Register

BIT

NAME

DESCRIPTION

[31:24]

PHI0[7:0]

Channel 0 sample instant adjust. PHI0 delays sampling instant on channel 0 by 32 XIN clock cycles per

LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).

[23:16]

PHI1[7:0]

Channel 1 sample instant adjust. PHI1 delays sampling instant on channel 1 by 32 XIN clock cycles per

LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).

[15:8]

PHI2[7:0]

Channel 2 sample instant adjust. PHI2 delays sampling instant on channel 2 by 32 XIN clock cycles per

LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).

[7:0]

PHI3[7:0]

Channel 3 sample instant adjust. PHI3 delays sampling instant on channel 3 by 32 XIN clock cycles per

LSB, up to 8192 cycles total (1.3μs resolution; 333μs range at XIN of 24.576MHz).

Table 4. Configuration Register

BIT

NAME

DESCRIPTION

SHDN

Shutdown bit. Set SHDN high to place the device in shutdown mode. In shutdown mode, the internal

oscillator, fault circuitry, and internal bandgap reference are turned off. Set SHDN low for normal operation.

RST

Reset bit. Set RST high to reset all registers to the default states except for the RST bit, and realign

sampling clocks and output data.

EN24BIT

Enable 24-bit resolution bit for the MAX11040K. Set EN24BIT high to enable the 24-bit data output. Set

EN24BIT low to enable 19-bit data output with device address and channel address tags. Tables 5 and 6

specify the Data register for both states of this bit. Set to 0 for MAX11060.

XTALEN

Internal oscillator enable bit. When using the on-chip crystal oscillator as the clock source, set XTALEN high

to enable the crystal oscillator and provide a buffered version of the crystal clock at the CLKOUT output.

When using an external clock source, set XTALEN low to disable the internal crystal oscillator and three-

state the CLKOUT output. Connect the external clock source to the XIN input.

FAULTDIS

Overvoltage fault-protection disable bit. Set FAULTDIS high to disable the overvoltage fault-protection

circuits. For FAULTDIS = 0, the absolute maximum input range is ±6V. Analog inputs beyond the fault-

detection threshold range trip the fault-protection circuits. The output remains clipped for a fault-recovery

time (typically < 1.57ms) after the inputs return within the fault-detection threshold range. For FAULTDIS =

1, the absolute maximum input range is only ±3.5V, but there is no fault-recovery delay. See the

Overvoltage Fault Detection and Recovery (FAULT) section.

PDBUF

PDBUF = 1 disables the internal reference buffer. Use this mode when an external reference is used;

otherwise, PDBUF should be set to 0 to enable the internal reference buffer.

[1:0]

Reserved

Must set to 0.

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